Virtual Memory, Paging, and TLB

Purpose

Explain virtual memory: paging, multi-level page tables, TLB role, page faults, and address translation — bridging OS kernels, embedded MPU, and performance analysis.

When to Use

• Understanding mmap, brk, and demand paging
• Debugging segfaults and guard pages
• Huge pages / TLB pressure tuning
• Contrasting Cortex-M MPU with full MMU systems

Workflow

1. Translation overview

Virtual address (VA)
├── TLB lookup → physical on hit
└── TLB miss → page table walk → fill TLB
        ├── valid PTE → physical address
        └── invalid → page fault (OS handles)

2. Page table (x86-64 4-level example)

CR3 → PML4 → PDPT → PD → PT → physical frame

Linux on x86_64 uses 4 KiB pages (default) and optional 2 MiB / 1 GiB huge pages.

3. Page fault types (simplified)

# Linux page fault stats
grep pgfault /proc/vmstat

4. TLB pressure

Large sparse address spaces + random pointer chasing → TLB misses dominate.

Mitigations:

• mmap huge pages (MAP_HUGETLB, madvise(MADV_HUGEPAGE))
• Smaller working set / better locality
• numactl --membind for NUMA

5. Embedded contrast (Cortex-M)

Many MCUs use MPU (region-based) not full paging — no TLB, fixed region count. Application processors use MMU + OS.

See skills/platform/riscv-privileged for Sv39/Sv48.

6. Userspace inspection (Linux)

cat /proc/self/maps
pmap -x $$

7. Agent usage

/virtual-memory-paging-and-tlb Explain why 4 KiB random access hurts TLB and hugepage helps

Common Problems

Related Skills

• skills/computer-architecture/memory-hierarchy-and-caches — cache after translation
• skills/kernel-dev/kernel-memory-management — kernel page allocator
• skills/kernel/os-dev-scratch — build paging from scratch
• skills/platform/riscv-privileged — Sv39 page tables
• skills/allocators/numa-programming — NUMA and migration